View WM8746SEDSR_762703.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

w
DESCRIPTION
WM8746 is a high performance 6-channel DAC designed for audio applications such as DVD, home theatre systems, and digital TV. The WM8746 supports data input word lengths from 16 to 32-bits and sampling rates up to 192kHz. The WM8746 can convert up to 6 channels at sample rates from 8 to 192kHz. Additionally WM8746 supports 2 channels at 192kHz and 4 channels at 96kHz simultaneously. The WM8746 consists of a serial interface port, digital interpolation filters, multi-bit sigma delta modulators and 6 DACs in a small 28-pin SSOP package. The WM8746 also includes a digitally controllable mute and attenuator function on each channel. The WM8746 supports a variety of connection schemes for audio DAC control. The serial control interface provides access to a wide range of features including on-chip mute, attenuation and phase reversal. A hardware controllable interface is also available. It is pin-compatible with the WM8736, (apart from RSTB pin which is typically unused). The WM8746 is an ideal device to interface to AC-3, DTS, and MPEG audio decoders for surround sound applications, or for use in "universal" high definition audio players supporting DVD-A formats.
WM8746
24-bit, 192kHz 6-Channel DAC with Volume Control
FEATURES
* * 6-Channel DAC Audio Performance - 106dB SNR (`A' weighted @ 48kHz) DAC - -95dB THD DAC Sampling Frequency: 8kHz - 192kHz 3-Wire Serial Control Interface Programmable Audio Data Interface Modes - * * * * * I2S, Left, Right Justified or DSP - 16/20/24/32 bit Word Lengths Independent Digital Volume Control on Each Channel with 127.5dB Range in 0.5dB Steps 3.0V - 5.5V Supply Operation 28-Pin SSOP Package Exceeds Dolby Class A Performance Requirements Pin Compatible with WM8736
* * *
APPLICATIONS
* * * DVD and DVD `Universal' Players Home theatre systems Digital broadcast receivers
BLOCK DIAGRAM
SCKI ML/I2S MC/IWL MD/DM MODE MUTE
WM8746
CONTROL INTERFACE ATC DEEMPH BCP PDWN PL[3:0] IWL[1:0] MUTE UPDATE LxA[23:0] LRP RxA[23:0] FMT[1:0] PDWN PDWN
PDWN
L0A[7:0] Digital Filter Sigma Delta Modulator Stereo DAC OUT0L GR0 OUT0R
BCKIN LRCIN LRCIN2 R0A[7:0] L1A[7:0] AUDIO INTERFACE DAC CHANNEL CONTROL R1A[7:0] DIN0 DIN1 DIN2 L2A[7:0]
Digital Filter
Sigma Delta Modulator
Stereo DAC
OUT1L GR1 OUT1R
Digital Filter
Sigma Delta Modulator
Stereo DAC
OUT2L GR2 OUT2R
R2A[7:0]
DVDD
DGND
AGND1
AGND2
AVDD1
AVDD2
CAP
WOLFSON MICROELECTRONICS plc
To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/
Production Data, March 2006, Rev 4.0
Copyright 2006 Wolfson Microelectronics plc
WM8746
Production Data
TABLE OF CONTENTS DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................3 ORDERING INFORMATION ..................................................................................3 PIN DESCRIPTION ................................................................................................4 ABSOLUTE MAXIMUM RATINGS.........................................................................5
DC ELECTRICAL CHARACTERISTICS ........................................................................ 6 AC ELECTRICAL CHARACTERISTICS ........................................................................ 6 TERMINOLOGY ............................................................................................................ 7 MASTER CLOCK TIMING ............................................................................................. 8 DIGITAL AUDIO INTERFACE TIMING.......................................................................... 8 DIGITAL CONTROL INTERFACE ................................................................................. 9
DEVICE DESCRIPTION.......................................................................................10
INTRODUCTION ......................................................................................................... 10 AUDIO DATA SAMPLING RATES............................................................................... 10 DIGITAL AUDIO INTERFACE ..................................................................................... 11 MODES OF OPERATION ........................................................................................... 14 SOFTWARE CONTROL MODES................................................................................ 15 HARDWARE CONTROL MODES ............................................................................... 21 SOFTWARE CONTROL INTERFACE......................................................................... 22
REGISTER MAP...................................................................................................23 DAC FILTER RESPONSES .................................................................................26 DIGITAL DE-EMPHASIS CHARACTERISTICS ...................................................27 RECOMMENDED EXTERNAL COMPONENTS ..................................................28
RECOMMENDED EXTERNAL COMPONENTS VALUES ........................................... 28
DECOUPLING APPLICATIONS INFORMATION ................................................29
SUPPLY PINS DESCRIPTION.................................................................................... 29 DC ELECTRICAL CHARACTERISTICS ...................................................................... 29 DECOUPLING EXAMPLES......................................................................................... 29
RECOMMENDED ANALOGUE LOW-PASS FILTER (OPTIONAL) ....................30 PACKAGE DIMENSIONS ....................................................................................31 IMPORTANT NOTICE ..........................................................................................32
ADDRESS: .................................................................................................................. 32
w
March 2006, PD Rev 4.0 2
WM8746 PIN CONFIGURATION
Production Data
ORDERING INFORMATION
DEVICE WM8746SEDS WM8746SEDS/R Note: Reel quantity = 2,000 TEMPERATURE RANGE -25 to +85oC -25 to +85oC PACKAGE 28-lead SSOP (Pb-free) 28-lead SSOP (Pb-free, tape and reel) MSL1 260C MOISTURE SENSITIVITY LEVEL MSL1 PEAK SOLDERING TEMPERATURE 260C
w
March 2006, PD Rev 4.0 3
WM8746 PIN DESCRIPTION
PIN 1 2 3 4 5 6 7 8 NAME DVDD SCKI BCKIN LRCIN DIN0 DIN1 DIN2 MODE TYPE Supply Digital input Digital input Digital input Digital input Digital input Digital input Digital input Internal pull-up Digital bidirectional Digital Positive Supply. System Clock Input Audio Data Bit Clock Input. DAC Sample Rate Clock Input Channel 0 Serial Audio Data Input. Channel 1 Serial Audio Data Input. Channel 2 Serial Audio Data Input. Control Method Selection Pin. Low = Software Mode High = Hardware Control Mode Mute Control Pin in PCM Mode. Input Low: Not Mute High: Mute Z: Automute 10 11 12 LRCIN2 DGND ML/I2S Digital input Internal pull-down Supply Digital input Internal pull-up Digital input Internal pull-up Digital input Supply Analogue output Analogue output Analogue input Analogue output Supply Analogue output Analogue input Analogue output Supply Analogue output Analogue input Analogue output Supply DESCRIPTION
Production Data
9
MUTE
Output (Automute Enabled) Low: Mute Off High: Mute On (Zero Flag)
2nd LRCIN for use in mixed 192kHz/96kHz operation (bit 2SPD = `hi') Digital GND Software mode: 3-Wire Serial Control Latch Hardware Mode: Input Format Selection: Software Mode: 3-Wire Serial Control Clock Input Hardware mode: Input Word Length Selection: Software mode: 3-Wire Serial Control Data Input Hardware mode: De-emphasis selection Analogue Positive DAC Reference Analogue Internal Mid-Rail Reference De-Coupling Point Left Channel 2 Output. Channel 2 Negative Reference. Right Channel 2 Output. Analogue GND Left Channel 1 Output. Channel 1 Negative Reference. Right Channel 1 Output. Analogue GND Left Channel 0 Output. Channel 0 Negative Reference. Right Channel 0 Output. Analogue VDD
13
MC/IWL
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Note: 1.
MD/DM AVDD2 CAP OUT2L GR2 OUT2R AGND1 OUT1L GR1 OUT1R AGND2 OUT0L GR0 OUT0R AVDD1
Digital input pins have Schmitt trigger input buffers
w
March 2006, PD Rev 4.0 4
WM8746 ABSOLUTE MAXIMUM RATINGS
Production Data
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION Digital supply voltage Analogue supply voltage Voltage range digital inputs Voltage range analogue inputs Master Clock Frequency Operating temperature range, TA Storage temperature after soldering -25C -65C MIN -0.3V -0.3V DGND -0.3V AGND -0.3V MAX +7V +7V DVDD +0.3V AVDD +0.3V 37MHz +85C +150C
w
March 2006, PD Rev 4.0 5
WM8746
DC ELECTRICAL CHARACTERISTICS
PARAMETER Digital supply range Analogue supply range Ground Difference DGND to AGND Analogue supply current Digital supply current Analogue supply current Digital supply current Analogue supply current Digital supply current Note: 1. The digital supply voltages must not exceed the analogue supply voltages. AVDD = 5V DVDD = 5V AVDD = 3.3V DVDD = 3.3V Power down, stop clock Power down, stop clock SYMBOL DVDD AVDD1, AVDD2 AGND, GR0,GR1, DGND -0.3 TEST CONDITIONS MIN 3.0 3.0 0 0 58 22 57 11 0.4 0.09 +0.3 TYP MAX 5.5 5.5
Production Data
UNIT V V V V mA mA mA mA mA mA
AC ELECTRICAL CHARACTERISTICS
Test Conditions AVDD = DVDD = 5V, AGND = 0V = DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated. PARAMETER Digital Logic Levels (TTL Levels) Input LOW level Input HIGH level Output LOW Output HIGH Analogue Reference Levels Reference voltage Potential divider resistance DAC Output (Load = 10k 50pF) 0dBFs Full scale output voltage SNR (Note 1,2,3) SNR (Note 1,2,3) SNR (Note 1,2,3) SNR (Note 1,2,3) At DAC outputs A-weighted, @ fs = 48kHz A-weighted @ fs = 96kHz A-weighted @ fs = 192kHz A-weighted, @ fs = 48kHz AVDD=DVDD=3.3V A-weighted @ fs = 96kHz AVDD=DVDD=3.3V Non `A' weighted @ fs = 48kHz AVDD=DVDD=5V 1kHz, 0dBFs 1kHz, -60dBFs -100 100 1.1 x AVDD1/5 106 105 105 103 Vrms dB dB dB dB VCAP RCAP (AVDD2GR2)/2 25k V VIL VIH VOL VOH IOL = 2mA IOH = 2mA 2.4 2.0 0.4 0.8 V V V V SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
SNR (Note 1,2,3)
103
dB
SNR (Note 1,2,3)
103
dB
THD (Note 1,2,3) THD+N (Dynamic range, Note 2) DAC channel separation
-95 -106 100
dB dB dB
w
March 2006, PD Rev 4.0 6
WM8746
Test Conditions AVDD = DVDD = 5V, AGND = 0V = DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated. PARAMETER Analogue Output Levels Output level Load = 10k, 0 dBFS, (AVDD=5.0V) Load = 10k, 0 dBFS, (AVDD=3.3V) Gain mismatch channel-to-channel Minimum resistance load To midrail or a.c. coupled To midrail or a.c. coupled (AVDD = 3.3V) Maximum capacitance load Output d.c. level Power On Reset (POR) POR threshold Notes: 1. 2. 2.0 5V or 3.3V 1.1 SYMBOL TEST CONDITIONS MIN TYP MAX
Production Data
UNIT Vrms
0.73
1 1 1
%FSR k k
100 (AVDD1AGND)/2
pF V
V
Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured `A' weighted over a 20Hz to 20kHz bandwidth. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. CAP decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance).
3.
TERMINOLOGY
1. 2. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band). Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other. Pass-Band Ripple - Any variation of the frequency response in the pass-band region.
3. 4. 5. 6.
w
March 2006, PD Rev 4.0 7
WM8746
MASTER CLOCK TIMING
tSCKIL SCKI tSCKIH tSCKIY
Production Data
Figure 1 Master Clock Timing Requirements Test Conditions AVDD = DVDD = 5V, AGND = GR = DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated. PARAMETER System Clock Timing Information
SCKI System clock pulse width high SCKI System clock pulse width low SCKI System clock cycle time SCKI Duty cycle
SYMBOL tSCKIH tSCKIL tSCKIY
TEST CONDITIONS
MIN 13 13 26 40:60
TYP
MAX
UNIT ns ns ns
60:40
Table 1 Master Clock Timing Requirements
DIGITAL AUDIO INTERFACE TIMING
tBCH BCLK tBCY DACLRC tDS DIN0/1/2 tDH tLRH tLRSU tBCL
Figure 2 PCM Digital Audio Data Timing Test Conditions AVDD = DVDD = 5V, AGND = GR = DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated. PARAMETER BCKIN cycle time BCKIN pulse width high BCKIN pulse width low LRCIN set-up time to BCKIN rising edge LRCIN hold time from BCKIN rising edge DIN0/1/2 set-up time to BCKIN rising edge DIN0/1/2 hold time from BCKIN rising edge Table 2 PCM Digital Audio Timing SYMBOL tBCY tBCH tBCL tLB tBL tDS tDH TEST CONDITIONS MIN 40 16 16 8 8 8 8 TYP MAX UNIT ns ns ns ns ns ns ns
Audio Data Input Timing Information
w
March 2006, PD Rev 4.0 8
WM8746
DIGITAL CONTROL INTERFACE
tMLL ML/I2S tMCY tMCH MC/IWL tMCL tSCS tCSS tMLH
Production Data
MD/DM tDSU tDHO
LSB
Figure 3 Control Interface Input Timing: 3-Wire Serial Control Mode Test Conditions AVDD = DVDD = 5V, AGND = GR = DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated. PARAMETER MC/IWL rising edge to ML/I2S rising edge MC/IWL pulse cycle time MC/IWL pulse width low MC/IWL pulse width high MD/DM to MC/IWL set-up time MC/IWL to MD/DM hold time ML/I2S pulse width low ML/I2S pulse width high ML/I2S rising to MC/IWL rising SYMBOL tSCS tMCY tMCL tMCH tDSU tDHO tMLL tMLH tCSS TEST CONDITIONS MIN 20 80 30 30 20 20 20 20 20 TYP MAX UNIT ns ns ns ns ns ns ns ns ns
Program Register Input Information
Table 3 Control Interface Input Timing Information: 3-Wire Serial Control Mode
w
March 2006, PD Rev 4.0 9
WM8746 DEVICE DESCRIPTION
INTRODUCTION
Production Data
WM8746 is a complete 6-channel stereo audio digital-to-analogue converter, including digital interpolation filter, multi-bit sigma delta with dither, and switched capacitor multi-bit stereo DAC and output smoothing filters. The device is implemented as three separate stereo DACs in a single package and controlled by a single interface. Each DAC has its own data input DIN0/1/2, and LRCIN, BCKIN and SCKI are shared between them. An additional LRCIN2 input is provided to allow for the front channels in a surround system to be run at higher sample rate than the other 4 channels (ie. 192kHz for front channels and 96kHz). In this mode the same SCKI is used for all channels, the front channels being run at twice the over-sampling rate of the other channels. Control of internal functionality of the device is by either hardware control (pin programmed) or software control (3-wire serial control interface). The MODE pin selects between hardware and software control. In software control mode, an SPI type interface is used. This interface may be asynchronous to the audio data interface. Control data will be re-synchronised to the audio processing internally. Operation using a system clock of 256fs, 384fs, 512fs or 768fs is provided, selection between clock rates being automatically detected. Sample rates (fs) from less than 8kHz to 96kHz are allowed, provided the appropriate system clock is input. Support is also provided for up to 192kHz using a system clock of 128fs or 192fs. The audio data interface supports right, left and I S interface formats along with a highly flexible DSP serial port interface. When in hardware mode, the three serial interface pins become control pins to allow selection of input data format type (I2S or right justified), input word length (16, 20, 24, or 32-bit) and de-emphasis functions.
2
AUDIO DATA SAMPLING RATES
In a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system's Master Clock. The external master system clock can be applied directly through the SCKI input pin with no software configuration necessary. Note that on the WM8746, SCKI is used to derive clocks for the DAC path. The DAC path consists of DAC sampling clock, DAC digital filter clock and DAC digital audio interface timing. In a system where there are a number of possible sources for the reference clock it is recommended that the clock source with the lowest jitter be used to optimise the performance of the DAC. The system clock for WM8746 supports audio sampling rates from 128fs to 768fs, where fs is the audio sampling frequency (LRCIN) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The system clock is used to operate the digital filters and the noise shaping circuits. The WM8746 has a system clock detection circuit that automatically determines the relationship between the system clock frequency and the sampling rate (to within +/- 32 system clocks). If greater than 32 clocks error, the interface defaults to 768fs and maintains the output level at the last sample. The system clock should be synchronised with LRCIN, although the WM8746 is tolerant of phase differences or jitter on this clock. Table 4 shows the typical system clock frequency inputs for the WM8746. SAMPLING RATE (FS) (LRCIN) 32kHz 44.1kHz 48kHz 96kHz 192kHz SYSTEM CLOCK FREQUENCY (MHZ) 128fs 4.096 5.6448 6.144 12.288 24.576 192fs 6.144 8.467 9.216 18.432 36.864 256fs 8.192 11.2896 12.288 24.576 Unavailable 384fs 12.288 16.9340 18.432 36.864 Unavailable 512fs 16.384 22.5792 24.576 Unavailable Unavailable 768fs 24.576 33.8688 36.864 Unavailable Unavailable
Table 4 System Clock Frequencies Versus Sampling Rate
w
March 2006, PD Rev 4.0 10
WM8746
DIGITAL AUDIO INTERFACE
Production Data
Audio data is applied to the internal DAC filters via the Digital Audio Interface. Five popular interface formats are supported: * * * * * Left Justified mode Right Justified mode I2S mode DSP Mode A DSP Mode B
All 5 formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits, except right justified that does not support 32 bit data. DIN0/1/2 and LRCIN are sampled on the rising, or falling edge of BCKIN. In left justified, right justified and I2S modes, the digital audio interface receives data on the DIN0/1/2 inputs. Audio Data for each stereo channel is time multiplexed with LRCIN indicating whether the left or right channel is present. LRCIN is also used as a timing reference to indicate the beginning or end of the data words. In left justified, right justified and I2S modes, the minimum number of BCKINs per LRCIN period is twice the selected word length. LRCIN must be high for at least the word length number of BCKINs and low for at least the same. Any mark to space ratio on LRCIN is acceptable provided the above requirements are met. The WM8746 will automatically detect when data with a LRCIN period of exactly 32 is sent, and select 16 bit mode - overriding any previously programmed word length. Word length will revert to the previously programmed value if a LRCIN period other than 32 is detected. In DSP Mode A or B, all 6 channels are time multiplexed onto DIN0. LRCIN is used as a frame sync signal to identify the MSB of the first word. The minimum number of BCKINs per LRCIN period is 6 times the selected word length. Any mark to space ratio is acceptable on LRCIN provided the rising edge is correctly positioned. (see Figure 7, Figure 8)
LEFT JUSTIFIED MODE
In left justified mode, the MSB is sampled on the first rising edge of BCKIN following a LRCIN transition. LRCIN is high during the left samples and low during the right samples.
1/fs
LEFT CHANNEL LRCIN
RIGHT CHANNEL
BCKIN
DIN0/1/2
1
2
3
n-2 n-1
n
1
2
3
n-2 n-1
n
MSB
LSB
MSB
LSB
Figure 4 Left Justified Mode Timing Diagram
w
March 2006, PD Rev 4.0 11
WM8746
RIGHT JUSTIFIED MODE
Production Data
In right justified mode, the LSB is sampled on the rising edge of BCKIN preceding a transition. LRCIN is high during the left samples and low during the right samples.
LRCIN
1/fs
LEFT CHANNEL LRCIN
RIGHT CHANNEL
BCKIN
DIN0/1/2
1
2
3
n-2 n-1
n
1
2
3
n-2 n-1
n
MSB
LSB
MSB
LSB
Figure 5 Right Justified Mode Timing Diagram
I2S MODE
In I2S mode, the MSB is sampled on the second rising edge of BCKIN following a LRCIN transition. LRCIN is low during the left samples and high during the right samples.
1/fs
LEFT CHANNEL LRCIN
RIGHT CHANNEL
BCKIN
1 BCKIN 1 BCKIN 3 n-2 n-1 n 1 2 3 n-2 n-1 n
DIN0/1/2
1
2
MSB
LSB
MSB
LSB
Figure 6 I S Mode Timing Diagram
2
DSP MODE A
In DSP mode A, the first bit is sampled on the BCKIN edge following the one which detects a low to high transition on LRCIN.
1 BCKIN 1/fs 1 BCKIN
LRCIN
BCKIN CHANNEL 0 LEFT DIN0
1 2 n-1 n 1 2
CHANNEL 0 RIGHT
n-1 n
CHANNEL 1 LEFT
1 2
CHANNEL 2 RIGHT
n-1 n
NO VALID DATA
MSB
LSB
Input Word Length (IWL)
Figure 7 DSP Mode A Timing Diagram
w
March 2006, PD Rev 4.0 12
WM8746
DSP MODE B
Production Data
In DSP mode B, the first bit is sampled on the BCKIN edge which detects a low to high transition on LRCIN.
1/fs
LRCIN
BCKIN CHANNEL 0 LEFT DIN0
1 2 n-1 n 1 2
CHANNEL 0 RIGHT
n-1 n
CHANNEL 1 LEFT
1 2
CHANNEL 2 RIGHT
n-1 n
NO VALID DATA
1
MSB
LSB
Input Word Length (IWL)
Figure 8 DSP Mode B Timing Diagram In both DSP modes, DAC0 left is always sent first, followed immediately by data words for the other 5 channels. No BCKIN edges are allowed between the data words. The word order is DAC0 left, DAC0 right, DAC1 left, DAC1 right, DAC2 left, DAC2 right.
SPLIT RATE MODE
The WM8746 can be used with differing sample rates on the front and rear channels. This allows extremely high quality audio to be played on the front two channels whilst the other channels use normal high quality data streams. This mode will only work with a front data rate of 192kHz and a rear rate of 96kHz but can be used with all the normal data formats except the two DSP modes and with the system at either 128fs or 192fs see Table 4. When running in split rate mode all the channels are clocked in using a common BCKIN; the front channels using LRCIN and all the other channels using LRCIN2 see Figure 9.
2/fs
LEFT CHANNEL LRCIN
RIGHT CHANNEL
LEFT CHANNEL
RIGHT CHANNEL
BCKIN
DIN0
12
n
12
n
12
n
12
n
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
LRCIN2
LEFT CHANNEL
RIGHT CHANNEL
DIN1/2
12
n
12
n
MSB
LSB
MSB
LSB
Figure 9 Split Rate Audio Mode Timing Diagram Notes: 1. Figure 9 shows the timing for left justified however this is similar for right justified and I2S. 2. The edges of LRCIN and LRCIN2 must be coincidental.
w
March 2006, PD Rev 4.0 13
WM8746
MODES OF OPERATION
Production Data
Control of the various modes of operation for the WM8746 is either by software control over the serial interface ,or by hard-wired pin control. Selection of software or hardware mode is via the MODE pin. The following functions may be controlled either via the serial control interface or by hard wiring of the appropriate pins. FUNCTION OPTIONS Input audio data format Right justified Left justified I2S format DSP formats 16 20 24 32 On Off On Off Normal Inverted Lch, Rch individually Lch, Rch common On Off SOFTWARE CONTROL DEFAULT VALUE PIN 8: MODE = 0 FMT = 00 (default) FMT = 01 FMT = 10 FMT = 11 IWL[1:0] = 00 IWL[1:0] = 01 IWL[1:0] = 10 (default) IWL[1:0] = 11 DEEMPH = 1 DEEMPH = 0 (Default) MUTE = 1 MUTE = 0 (default) LRP = 0 (default) LRP = 1 ATC = 0; 0dB (default) ATC = 1 IZD = 1 IZD = 0 (default) Automute function controlled from MUTE pin low = never mute floating = automute enable high = mute Run SCKI Stop SCKI Not available in hardware mode HARDWARE CONTROL BEHAVIOUR PIN 8: MODE = 1 Pin 12, 13: ML/I2S, MC/IWL = 00, 01 or 10 Not available in hardware mode Pin 12, 13: ML/I2S, MC/IWL = 11 Not available in hardware mode Pin 12, 13: ML/I2S, MC/IWL = 00 (RJ) Pin 12, 13: ML/I2S, MC/IWL = 01 (RJ) Pin 12, 13: ML/I2S, MC/IWL = 10 (RJ) Pin 12, 13: ML/I2S, MC/IWL = 11 (I2S) Pin 14: MD/DM = 1 Pin 14: MD/DM = 0 Pin 9: MUTE = 1 Pin 9: MUTE = 0 Not available in hardware mode, default value set Not available in hardware mode, gain defaults to 0dB
Input word length
De-emphasis selection
Mute
Input LRCIN polarity Volume control
Infinite zero detect
Power down DAC output control
Chip on Chip off See Table 6 for all options
PWDN = 0 (default) PWDN = 1 Default is PL[3:0] = 1001, stereo mode
Table 5 Control Function Summary
w
March 2006, PD Rev 4.0 14
WM8746
SOFTWARE CONTROL MODES
DIGITAL AUDIO INTERFACE CONTROL REGISTERS
Interface format is selected via the FMT[1:0] register bits: REGISTER ADDRESS 0000011 Interface Control BIT 1:0 LABEL FMT[1:0] DEFAULT 00
Production Data
DESCRIPTION Interface format Select 00 : right justified mode 01: left justified mode 10: I2S mode 11: DSP mode A or B
In left justified, right justified or I2S modes, the LRP register bit controls the polarity of LRCIN. If this bit is set high, the expected polarity of LRCIN will be the opposite of that shown Figure 4, Figure 5 and Figure 6. Note that if this feature is used as a means of swapping the left and right channels, a 1 sample phase difference will be introduced. REGISTER ADDRESS 0000011 Interface Control BIT 2 LABEL LRP DEFAULT 0 DESCRIPTION LRCIN Polarity 0 : normal LRCIN polarity 1: inverted LRCIN polarity
In DSP modes, the LRCIN register bit is used to select between early and late modes: REGISTER ADDRESS 0000011 Interface Control BIT 2 LABEL LRP DEFAULT 0 DESCRIPTION DSP Format 0: Mode A 1: Mode B
By default, LRCIN and DIN0/1/2 are sampled on the rising edge of BCKIN and should ideally change on the falling edge. Data sources which change LRCIN and DIN0/1/2 on the rising edge of BCKIN can be supported by setting the BCP register bit. Setting BCP to 1 inverts the polarity of BCKIN to the inverse of that shown in Figure 4, Figure 5, Figure 6, Figure 7 and Figure 8. REGISTER ADDRESS 0000011 Interface Control BIT 3 LABEL BCP DEFAULT 0 DESCRIPTION BCKIN Polarity 0 : normal BCKIN polarity 1: inverted BCKIN polarity
The IWL[1:0] bits are used to control the input word length. REGISTER ADDRESS 0000011 Interface Control BIT 5:4 LABEL IWL[1:0] DEFAULT 10 DESCRIPTION Input Word Length 00 : 16 bit data 01: 20 bit data 10: 24 bit data 11: 32 bit data
Note: If 32-bit mode is selected in right justified mode, the WM8746 defaults to 24 bits. In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If the DAC is programmed to receive 16 or 20 bit data, the WM8746 pads the unused LSBs with zeros. If the DAC is programmed into 32 bit mode, the 8 LSBs are ignored. The PHASE bits control the orientation of the data output of the three stereo channels. By default all the channels are non-inverting. REGISTER ADDRESS 0000011 Interface Control BIT 8:6 LABEL PHASE DEFAULT 000 DESCRIPTION Output phase direction 1 in bit 6 reverses OUT0L/R. 1 in bit 7 reverses OUT1L/R. 1 in bit 8 reverses OUT2L/R.
w
March 2006, PD Rev 4.0 15
WM8746
MUTE MODES
Setting the MUTE register bit will apply a 'soft' mute to the input of the digital filters: REGISTER ADDRESS 0000010 DAC Channel Control BIT 0 LABEL MUTE DEFAULT 0
Production Data
DESCRIPTION Soft Mute select 0 : Normal Operation 1: Soft mute all channels
1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 0 0.001 0.002 0.003 Time(s) 0.004 0.005 0.006
Figure 10 Application and Release of Soft Mute Figure 10 shows the application and release of MUTE whilst a full amplitude sinusoid is being played at 48kHz sampling rate. When MUTE (lower trace) is asserted, the output (upper trace) begins to decay exponentially from the DC level of the last input sample. The output will decay towards VCAP with a time constant of approximately 64 input samples. If MUTE is applied for 1024 or more input samples, the outputs will be connected directly to VCAP - this feature can be disabled using the IZD (infinite zero detect) bit. When MUTE is de-asserted, the output will restart almost immediately from the current input sample. Note that all other means of muting the DAC channels: setting the PL[3:0] bits to 0, setting the PWDN bit or setting attenuation to 0 will cause much more abrupt muting of the output. Setting the IZD register bit will enable the infinite zero detect feature: REGISTER ADDRESS 0000010 DAC Channel Control BIT 4 LABEL IZD DEFAULT 0 DESCRIPTION Internal Analogue Mute Disable 0 : Disable Analogue Mute 1: Enable Analogue Mute
With IZD=1, applying MUTE for 1024 consecutive input samples will cause all outputs to be connected directly to VCAP. This also happens if 2048 consecutive zero input samples are applied to all 6 channels, and IZD=0. It will be removed as soon as any channel receives a non-zero input. The MUTE pin can be used as an input. In this case it performs the same function as the MUTE register bit. Driving the MUTE pin high will apply a 'soft' mute. Driving it low again, will remove the MUTE immediately. Note that this hardware mute feature doesn't require the MODE pin to be set high.
w
March 2006, PD Rev 4.0 16
WM8746
MUTE PIN 0 1 Floating Normal Operation Mute all DAC channels MUTE becomes an output to indicate when IZD occurs. H = IZD detected (MUTE enabled) L = IZD not detected (MUTE disabled) DESCRIPTION
Production Data
A diagram showing how the various MUTE modes interact is shown below in Figure 11.
IZD (Register Bit) AUTOMUTED (Internal Signal) 10k MUTE PIN SOFTMUTE (Internal Signal)
MUTE (Register Bit)
Figure 11 Selection Logic for MUTE Modes The MUTE pin behaves as a bi-directional function, that is, as an input to select MUTE or NOTMUTE, or as an output indication of automute operation. MUTE is active high; taking the pin high causes the filters to soft mute, ramping down the audio signal over a few milliseconds. Taking MUTE low again allows data into the filter. The automute function detects a series of zero value audio samples of 1024 samples long being applied to all 6 channels. After such an event, a latch is set whose output (AUTOMUTED) is wire OR'ed through a 10kohm resistor to the MUTE pin. Thus if the MUTE pin is not being driven, the automute function will assert MUTE. If MUTE is tied low, AUTOMUTED is overridden and will not mute. If MUTE is driven from a source follower, or diode, then both MUTE and automute functions are available. If MUTE is not driven, AUTOMUTED appears as a weak output (10k source impedance) so can be used to drive external mute circuits. The automute signal is AND'ed with IZD, this qualified mute signal then being OR'ed into the SOFTMUTE control. Therefore, in software mode, automute operation may be controlled with the IZD control bit.
DE-EMPHASIS MODE
Setting the DEEMPH register bit puts all the digital filters into de-emphasis mode: REGISTER ADDRESS 0000010 DAC Channel Control BIT 1 LABEL DEEMPH DEFAULT 0 DESCRIPTION De-emphasis mode select: 0 : Normal Mode 1: De-emphasis Mode
Refer to Figure 18 - Figure 23 for details of the De-Emphasis filtering effects at different sample rates. In hardware mode (MODE=1) driving the MD/DM pin high has the same effect as setting the DEEMPH bit: MODE PIN 0 1 1 MD/DM PIN ignored 0 1 Normal Mode De-Emphasis Mode DESCRIPTION De-Emphasis controlled from DEEMPH register bit
w
March 2006, PD Rev 4.0 17
WM8746
POWERDOWN MODE
Production Data
Setting the PWDN register bit immediately connects all outputs to VCAP and selects a low power mode. All trace of the previous input samples is removed, but all control register settings are preserved. When PWDN is cleared again the first 16 input samples will be ignored as the FIR will repeat it's power-on initialisation sequence. REGISTER ADDRESS 0000010 DAC Channel Control BIT 2 LABEL PWDN DEFAULT 0 DESCRIPTION Power Down Mode Select: 0 : Normal Mode 1: Power Down Mode
ATTENUATOR CONTROL MODE
Setting the ATC register bit causes the left channel attenuation settings to be applied to both left and right channels for all three pairs of DACs from the next audio input sample. No update to the attenuation registers is required for ATC to take effect. REGISTER ADDRESS 0000010 DAC Channel Control BIT 3 LABEL ATC DEFAULT 0 DESCRIPTION Attenuator Control Mode: 0 : Right channels use Right attenuations 1: Right Channels use Left Attenuations
DAC OUTPUT CONTROL
The DAC output control word determines how the left and right inputs to the audio Interface are applied to the left and right DACs: REGISTER ADDRESS 0000010 DAC Control BIT 8:5 LABEL PL[3:0] DEFAULT 1001 PL[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Table 6 Input to Output Control DESCRIPTION Left Output Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Right Output Mute Mute Mute Mute Left Left Left Left Right Right Right Right (L+R)/2 (L+R)/2 (L+R)/2 (L+R)/2
w
March 2006, PD Rev 4.0 18
WM8746
ATTENUATION CONTROL
Production Data
Each DAC channel can be attenuated digitally before being applied to the digital filter. Attenuation is 0dB by default but can be set between 0 and 127.5dB in 0.5dB steps using the 8 Attenuation control bits. All attenuation registers are double latched allowing new values to be pre-latched to several channels before being updated synchronously. Setting the UPDATE bit on any attenuation write will cause all pre-latched values to be immediately applied to the DAC channels. A master attenuation register is also included, allowing all attenuations to be set to the same value in a single write. REGISTER ADDRESS 0000000 Attenuation DACL0 BIT 7:0 8 LABEL L0A[7:0] UPDATE DEFAULT 11111111 (0dB) Not latched DESCRIPTION Attenuation data for DACL0 in 0.5dB steps, see Table 8. Controls simultaneous update of all Attenuation Latches 0: Store DACL0 in intermediate latch (no change to output) 1: Store DACL0 and update attenuation on all channels. Attenuation data for DACR0 in 0.5dB steps, see Table 8. Controls simultaneous update of all Attenuation Latches 0: Store DACR0 in intermediate latch (no change to output) 1: Store DACR0 and update attenuation on all channels. Attenuation data for DACL1 in 0.5dB steps, see Table 8. Controls simultaneous update of all Attenuation Latches 0: Store DACL1 in intermediate latch (no change to output) 1: Store DACL1 and update attenuation on all channels. Attenuation data for DACR1 in 0.5dB steps, see Table 8. Controls simultaneous update of all Attenuation Latches 0: Store DACR1 in intermediate latch (no change to output) 1: Store DACR1 and update attenuation on all channels. Attenuation data for DACL2 in 0.5dB steps, see Table 8. Controls simultaneous update of all Attenuation Latches 0: Store DACL2 in intermediate latch (no change to output) 1: Store DACL2 and update attenuation on all channels. Attenuation data for DACR2 in 0.5dB steps, see Table 8. Controls simultaneous update of all Attenuation Latches 0: Store DACR2 in intermediate latch (no change to output) 1: Store DACR2 and update attenuation on all channels. Attenuation data for all channels in 0.5dB steps, see Table 8. Controls simultaneous update of all Attenuation Latches 0: Store MASTA[7:0] in all intermediate latches (no change to output) 1: Store MASTA[7:0] and update attenuation on all channels.
0000001 Attenuation DACR0
7:0 8
R0A[7:0] UPDATE
11111111 (0dB) Not latched
0000100 Attenuation DACL1
7:0 8
L1A[7:0] UPDATE
11111111 (0dB) Not latched
0000101 Attenuation DACR1
7:0 8
R1A[7:0] UPDATE
11111111 (0dB) Not latched
0000110 Attenuation DACL2
7:0 8
L2A[7:0] UPDATE
11111111 (0dB) Not latched
0000111 Attenuation DACR2
7:0 8
R2A[7:0] UPDATE
11111111 (0dB) Not latched
0001000 Master Attenuation (all channels)
7:0 8
MASTA[7:0] UPDATE
11111111 (0dB) Not latched
Table 7 Attenuation Register Map Note: The UPDATE bit is not latched. If UPDATE=0, the Attenuation value will be written to the pre-latch but not applied to the relevant DAC. If UPDATE=1, all pre-latched values will be applied from the next input sample. Writing to MASTA[7:0] overwrites any values previously sent to L0A[7:0], L1A[7:0], L2A[7:0], R0A[7:0], R1A[7:0], R2A[7:0].
w
March 2006, PD Rev 4.0 19
WM8746
DAC OUTPUT ATTENUATION
Production Data
Register bits [7:0] of L0A and R0A control the left and right channel attenuation of DAC 0. Register bits [7:0] of L1A and R1A control the left and right channel attenuation of DAC 1. Register bits [7:0] of L2A and R2B control the left and right channel attenuation of DAC 2. Register bits [7:0] of MASTA are a register that can be used to control attenuation of all channels. Table 8 shows how the attenuation levels are selected from the 8-bit words. XA[7:0] 00(hex) 01(hex) : : : FE(hex) FF(hex) Table 8 Attenuation Control Levels ATTENUATION LEVEL -dB (mute) -127.5dB : : : -0.5dB 0dB
EXTENDED INTERFACE CONTROL
It is possible to run the WM8746 channels at different rates with the front two channels running at twice the rate of the rear four channels. In this mode which is enabled by bit 0 of register 9, the interface runs at the faster data rate but pin 10 (LRCIN2) acts as the framing LRCIN for the rear channels see Figure 9. REGISTER ADDRESS 0001001 Split rate mode BIT 0 LABEL 2SPD DEFAULT 0 DESCRIPTION Activates the split rate mode 0: Normal operation 1: Split rate operation
When the WM8746 receives updates to the volume levels it will, by default, wait for the signal to pass through the VCAP voltage level before applying the change to the output. This zero cross detect function ensures that minimal distortion is seen on the output when the volume is changed and is applied separately to each channel. REGISTER ADDRESS 0001001 Zero crossing detect BIT 1 LABEL ZCD DEFAULT 0 DESCRIPTION Controls the ZCD 0: Enabled 1: Disabled
w
March 2006, PD Rev 4.0 20
WM8746
HARDWARE CONTROL MODES
Production Data
When the MODE pin is held high the following hardware modes of operation are available.
MUTE AND AUTOMUTE OPERATION
Pin 9 (MUTE) controls selection of MUTE directly, and can be used to enable and disable the automute function, or as an output of the automuted signal.
AUTOMUTED (Internal Signal) 10k MUTE PIN SOFTMUTE (Internal Signal)
Figure 12 Mute Circuit Operation The MUTE pin behaves as a bi-directional function, that is, as an input to select MUTE or NOTMUTE, or as an output indication of automute operation. MUTE is active high; taking the pin high causes the filters to soft mute, ramping down the audio signal over a few milliseconds. Taking MUTE low again allows data into the filter. The automute function detects a series of zero value audio samples of 1024 samples long being applied to all 6 channels. After such an event, a latch is set whose output (AUTOMUTED) is wire OR'ed through a 10kohm resistor to the MUTE pin. Thus if the MUTE pin is not being driven, the automute function will assert MUTE. If MUTE is tied low, AUTOMUTED is overridden and will not mute. If MUTE is driven from a source follower, or diode, then both MUTE and automute functions are available. If MUTE is not driven, AUTOMUTED appears as a weak output (10k source impedance) so can be used to drive external mute circuits.
ML/I2S AND MC/IWL INPUT FORMAT SELECTION
In hardware mode, pins 12 and 13 become input controls for selection of input data format type and input data word length, see Table 5. I2S mode is designed to support any word length provided enough bit clocks are sent. ML/I2S 0 0 1 1 MC/IWL 0 1 0 1 INPUT DATA MODE 16-bit right justified 20-bit right justified 24-bit right justified I2S mode
Table 9 Control of Input Data Format Type and Input Data Word Length
MD/DM DE-EMPHASIS
In hardware mode, pin 14 becomes an input control for selection of de-emphasis filtering to be applied. See Table 5. MD/DM 0 1 Table 10 De-emphasis Control DE-EMPHASIS MODE De-emphasis off De-emphasis on
w
March 2006, PD Rev 4.0 21
WM8746
SOFTWARE CONTROL INTERFACE
Production Data
The software control interface uses a 3-wire serial control interface. Selection of interface format is achieved by setting the state of the MODE pin. MODE 0 1 INTERFACE FORMAT Software Control Mode Hardware Control Mode
Table 11 Control Interface Mode Selection
3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE
The WM8746 can be controlled using a 3-wire serial interface. MD/DM is used for the program data, MC/IWL is used to clock in the program data and ML/I2S is use to latch in the program data. The 3wire interface protocol is shown in Figure 13.
ML/I2S
MC/IWL
MD/DM
A6
A5
A4
A3
A2
A1
A0
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 13 3-wire Serial Interface Notes: 1. 2. A[6:0] are Control Address Bits D[8:0] are Control Data Bits
w
March 2006, PD Rev 4.0 22
WM8746 REGISTER MAP
Production Data
The complete register map is shown below. The detailed description can be found in the relevant text of the device description. There are 9 registers with 9 bits per register. These can be controlled using the Control Interface. A6 M0 M1 M2 M3 M4 M5 M6 M7 M8 M9
0 0 0 0 0 0 0 0 0 0
A5
0 0 0 0 0 0 0 0 0 0
A4
0 0 0 0 0 0 0 0 0 0
A3
0 0 0 0 0 0 0 0 1 1
A2
0 0 0 0 1 1 1 1 0 0
A1
0 0 1 1 0 0 1 1 0 0
A0
0 1 0 1 0 1 0 1 0 1
D8
UPDATE UPDATE PL3 REV2 UPDATE UPDATE UPDATE UPDATE
D7
L0A7 R0A7 PL2 REV1 L1A7 R1A7 L2A7 R2A7
D6
L0A 6 R0A 6 PL1 REV0 L1A 6 R1A 6 L2A 6 R2A 6
D5
L0A 5 R0A 5 PL0 IWL1 L1A 5 R1A 5 L2A 5 R2A 5
D4
L0A 4 R0A 4 IZD IWL0 L1A 4 R1A 4 L2A 4 R2A 4
D3
L0A 3 R0A 3 ATC BCP L1A 3 R1A 3 L2A 3 R2A 3
D2
L0A 2 R0A 2
D1
L0A 1 R0A 1
D0
L0A 0 R0A 0 MUTE FMT0 L1A 0 R1A 0 L2A 0 R2A 0
PDWN DEEMPH LRP L1A 2 R1A 2 L2A 2 R2A 2 FMT1 L1A 1 R1A 1 L2A 1 R2A 1
UPDATE MASTA7 MASTA 6 MASTA 5 MASTA 4 MASTA 3 MASTA 2 MASTA 1 MASTA 0 0 0 0 0 0 0 0 ZCD 2SPD
Table 12 Register Map
REGISTER ADDRESS 0000000 Attenuation DACL0
BIT 7:0
LABEL L0A[7:0]
DEFAULT 11111111 (0dB) Not latched
DESCRIPTION Attenuation level of left channel DACL0 in 0.5dB steps, see Table 8.
8
UPDATE
Controls simultaneous update of all Attenuation Latches 0: Store DACL0 in intermediate latch (no change to output) 1: Store DACL0 and update attenuation on all channels. Attenuation level of left channel DACR0 in 0.5dB steps, see Table 8.
0000001 Attenuation DACR0
7:0
R0A[7:0]
11111111 (0dB) Not latched
8
UPDATE
Controls simultaneous update of all Attenuation Latches 0: Store DACR0 in intermediate latch (no change to output) 1: Store DACR0 and update attenuation on all channels.
w
March 2006, PD Rev 4.0 23
WM8746
REGISTER ADDRESS 0000010 DAC Control BIT 0 LABEL MUTE DEFAULT 0 DESCRIPTION Left and Right DACs soft mute control 0: No Mute 1: Mute
Production Data
1
DEEMPH
0
De-emphasis Control 0: Normal Response (see Figure 14 - Figure 17) 1: De-emphasis Response (see Figure 18 - Figure 23) Left and Right DACs Power-down Control 0: All DACs running, output is active 1: All DACs in power saving mode, output muted Attenuator Control 0: All DACs use attenuations as programmed. 1: Right chan. DACs use corresponding left DAC attenuations Infinite zero detection circuit control and automute control 0: Infinite zero detect disabled 1: Infinite zero detect enabled DAC Output Control PL[3:0] Left Output Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Right Output Mute Mute Mute Mute Left Left Left Left PL[3:0] Left Output Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Right Output Right Right Right Right (L+R)/2 (L+R)/2 (L+R)/2 (L+R)/2
2
PWDN
0
3
ATC
0
4
IZD
0
8:5
PL[3:0]
1001
0000 0001 0010 0011 0100 0101 0110 0111 0000011 Interface Control 1:0 FMT[1:0] 00
1000 1001 1010 1011 1100 1101 1110 1111
Interface format select 00: right justified mode 01: left justified mode 10: I2S mode 11: DSP Mode A or B LRCIN Polarity or LRCIN Phase Left Justified / Right Justified / I S 0: Standard LRCIN Polarity 1: Inverted LRCIN Polarity
2
2
LRP
0
DSP Mode 0: DSP Mode A 1: DSP Mode B
3
BCP
0
BCKIN Polarity 0: Normal (DIN[2:0] and LRCIN sampled on rising edge) 1: Inverted (DIN[2:0] and LRCIN sampled on falling edge) Input Word Length 00: 16-bit Mode 01: 20-bit Mode 10: 24-bit Mode 11: 32-bit Mode (not supported in right justified mode) Controls the output phase of the three stereo channels Bit 6 reverses the phase of data output on OUT0L/R. Bit 7 reverses the phase of data output on OUT1L/R. Bit 8 reverses the phase of data output on OUT2L/R.
5:4
WL[1:0]
10
8:6
PHASE
000
w
March 2006, PD Rev 4.0 24
WM8746
REGISTER ADDRESS 0000100 Attenuation DACL1 BIT 7:0 LABEL L1A[7:0] DEFAULT 11111111 (0dB) Not latched DESCRIPTION
Production Data
Attenuation level of left channel DACL1 in 0.5dB steps. See Table 8
8
UPDATE
Controls simultaneous update of all Attenuation Latches 0: Store DACL1 in intermediate latch (no change to output) 1: Store DACL1 and update attenuation on all channels. Attenuation level of right channel DACR1 in 0.5dB steps, see Table 8.
0000101 Attenuation DACR1
7:0
R1A[7:0]
11111111 (0dB) Not latched
8
UPDATE
Controls simultaneous update of all Attenuation Latches 0: Store DACR1 in intermediate latch (no change to output) 1: Store DACR1 and update attenuation on all channels. Attenuation level of left channel DACL2 in 0.5dB steps, see Table 8.
0000110 Attenuation DACL2
7:0
L2A[7:0]
11111111 (0dB) Not latched
8
UPDATE
Controls simultaneous update of all Attenuation Latches 0: Store DACL2 in intermediate latch (no change to output) 1: Store DACL2 and update attenuation on all channels. Attenuation level of right channel DACR2 in 0.5dB steps, see Table 8.
0000111 Attenuation DACR2
7:0
R2A[7:0]
11111111 (0dB) Not latched
8
UPDATE
Controls simultaneous update of all Attenuation Latches 0: Store DACR2 in intermediate latch (no change to output) 1: Store DACR2 and update attenuation on all channels. Attenuation data for all channels in 0.5dB steps, see Table 8.
0001000 Master Attenuation (all channels)
7:0
MASTA[7:0]
11111111 (0dB) Not latched
8
UPDATE
Controls simultaneous update of all Attenuation Latches 0: Store MASTA[7:0] in all intermediate latches (no change to output) 1: Store DACR0 and update attenuation on all channels Activates the split rate mode where the front channels run at 192kHz and the rear four channels run at 96kHz. 0: Normal operation. 1: Split rate operation. Controls the operation of the zero crossing detect mechanism which ensures that the volume is only updated on each channel when the signal passes through midrail. 0: Enable zero detect. 1: Disable zero detect.
0001001 Extended interface control
0
2SPD
0
1
ZCD
0
Table 13 Register Map Description
w
March 2006, PD Rev 4.0 25
WM8746 DIGITAL FILTER CHARACTERISTICS
PARAMETER Passband Stopband Passband Ripple Stopband Attenuation Table 14 Digital Filter Characteristics f > 0.555fs SYMBOL TEST CONDITIONS 0.05 dB -3dB MIN 0.444fs 0.487fs 0.05 -60 TYP MAX
Production Data
UNIT dB dB dB
DAC FILTER RESPONSES
0.2 0 0.15 -20 0.1
Response (dB)
Response (dB)
-40
0.05 0 -0.05 -0.1
-60
-80
-100
-0.15 -0.2 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5
-120
Figure 14 DAC Digital Filter Frequency Response - 44.1, 48 and 96kHz
Figure 15 DAC Digital Filter Ripple -44.1, 48 and 96kHz
0.2 0 0 -20
Response (dB)
Response (dB)
-0.2
-40
-0.4
-60
-0.6
-0.8 -80 -1 0 0.2 0.4 0.6 Frequency (Fs) 0.8 1 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5
Figure 16 DAC Digital Filter Frequency Response - 192kHz
Figure 17 DAC Digital Filter Ripple - 192 kHz
w
March 2006, PD Rev 4.0 26
WM8746 DIGITAL DE-EMPHASIS CHARACTERISTICS
0 1 0.5 -2 0
Production Data
Response (dB)
-4
Response (dB)
-0.5 -1 -1.5 -2
-6
-8 -2.5 -10 0 2 4 6 8 10 Frequency (kHz) 12 14 16 -3 0 2 4 6 8 10 Frequency (kHz) 12 14 16
Figure 18 De-Emphasis Frequency Response (32kHz)
0
Figure 19 De-Emphasis Error (32kHz)
0.4 0.3
-2 0.2
Response (dB)
Response (dB)
-4
0.1 0 -0.1 -0.2
-6
-8 -0.3 -10 0 5 10 Frequency (kHz) 15 20 -0.4 0 5 10 Frequency (kHz) 15 20
Figure 20 De-Emphasis Frequency Response (44.1kHz)
0
Figure 21 De-Emphasis Error (44.1kHz)
1 0.8
-2
0.6 0.4
Response (dB)
-4
Response (dB)
0.2 0 -0.2 -0.4
-6
-8
-0.6 -0.8
-10 0 5 10 15 Frequency (kHz) 20
-1 0 5 10 15 Frequency (kHz) 20
Figure 22 De-Emphasis Frequency Response (48kHz)
Figure 23 De-Emphasis Error (48kHz)
w
March 2006, PD Rev 4.0 27
WM8746
APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS
Production Data
Figure 24 External Components Diagram
RECOMMENDED EXTERNAL COMPONENTS VALUES
COMPONENT REFERENCE C1 and C5 C2 to C4 C6 to C11 C12 C13 C14 R1 SUGGESTED VALUE 10F 0.1F 10F 0.1F 10F 10F 33 Filtering for AVDD2. Omit if AVDD low noise. Filtering for AVDD2. Use 0 if AVDD low noise. DESCRIPTION De-coupling for DVDD and AVDD1. De-coupling for DVDD and AVDD1. Output AC coupling caps to remove midrail DC level from outputs. Reference de-coupling capacitors for CAP pin.
Table 15 External Components Description
w
March 2006, PD Rev 4.0 28
WM8746 DECOUPLING APPLICATIONS INFORMATION
SUPPLY PINS DESCRIPTION
PIN 1 11 15 16 20 24 28 NAME DVDD DGND AVDD2 CAP AGND1 AGND2 AVDD1 TYPE Supply Supply Supply Analogue output Supply Supply Supply Digital Positive Supply. Digital GND Analogue Positive DAC Reference Analogue Internal Mid-Rail Reference De-Coupling Point Analogue GND Analogue GND Analogue VDD DESCRIPTION
Production Data
DC ELECTRICAL CHARACTERISTICS
PARAMETER Analogue supply current Digital supply current Analogue supply current Digital supply current SYMBOL TEST CONDITIONS AVDD = 5V DVDD = 5V AVDD = 3.3V DVDD = 3.3V MIN TYP 58 22 57 11 MAX UNIT mA mA mA mA
For proper decoupling, 0.1F surface-mount ceramic capacitors are recommended for AVDD1, AVDD2, DVDD and CAP. Also recommended are 10F capacitors for AVDD, DVDD and CAP. These are a general guideline and are dependent on the amount of noise present in the system. If there is excessive noise on the supply, such as may be present in a commercial DVD receiver with motors and switching amplifiers, additional filtering will be required. The supply AVDD2 is the reference voltage for the DAC. It has no supply noise rejection, so any noise on this pin will affect the DAC outputs. There is not much current drawn on this supply pin. Supply AVDD1 does have supply rejection and draws most of the analogue supply current.
DECOUPLING EXAMPLES
Figure 25 Decoupling Example 1 In Figure 25, there is a single analogue supply that is fairly noisy. The AVDD1 and DVDD pins can tolerate this, but the AVDD2 needs additional filtering. The schematic illustrates a suitable solution.
w
March 2006, PD Rev 4.0 29
WM8746
Production Data It is important that the supply pins are connected correctly. If AVDD1 and AVDD2 pins had both been connected to the 10 resistor, the performance would be worse. The value of 10 is too high and will cause an increase in THD. This is because currents drawn by AVDD1 will affect the reference voltage on AVDD2. A full-scale output FFT plot will show increased harmonics, because the output current drawn modulates the reference voltage. 4.7F ceramic capacitors are becoming available in 0805 package with Y5V dielectric. Whilst they do not have quite as good performance as 10F, it is possible to use them instead. Their capacitance goes down significantly with supply voltage, but at 3.3V (VDD) and 1.65V (CAP pin), the drop is not too great, if a 10V-rated part is used. As they are already in a low-inductance package, the 0.1F is no longer necessary. See Figure 26 for an example.
Figure 26 Decoupling Example 2
RECOMMENDED ANALOGUE LOW-PASS FILTER (OPTIONAL)
4.7k 4.7k
+VS
_
10u F 51 1.8k 7.5K
+
+
1.0nF 10k 680pF -VS
Figure 27 Recommended Low Pass Filter (Optional)
w
March 2006, PD Rev 4.0 30
WM8746 PACKAGE DIMENSIONS
DS: 28 PIN SSOP (10.2 x 5.3 x 1.75 mm)
Production Data
DM007.E
b
28
e
15
E1
E
1
D
14
GAUGE PLANE
c A A2 A1
L
0.25
L1
-C0.10 C
SEATING PLANE
Symbols A A1 A2 b c D e E E1 L L1 REF: MIN ----0.05 1.65 0.22 0.09 9.90 7.40 5.00 0.55 0
o
Dimensions (mm) NOM --------1.75 0.30 ----10.20 0.65 BSC 7.80 5.30 0.75 1.25 REF o 4 JEDEC.95, MO-150
MAX 2.0 0.25 1.85 0.38 0.25 10.50 8.20 5.60 0.95 8
o
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM. D. MEETS JEDEC.95 MO-150, VARIATION = AH. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
w
March 2006, PD Rev 4.0 31
WM8746 IMPORTANT NOTICE
Production Data
Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM's standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical components in life support devices or systems without the express written approval of an officer of the company. Life support devices or systems are devices or systems that are intended for surgical implant into the body, or support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be reasonably expected to result in a significant injury to the user. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of WM covering or relating to any combination, machine, or process in which such products or services might be or are used. WM's publication of information regarding any third party's products or services does not constitute WM's approval, license, warranty or endorsement thereof.
Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use.
Resale of WM's products or services with statements different from or beyond the parameters stated by WM for that product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use.
ADDRESS:
Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom
Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com
w
March 2006, PD Rev 4.0 32

▲Up To Search▲

Price & Availability of WM8746SEDSR

	To Download WM8746SEDSR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .